Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

Some would have ASIC design teams pass their designs over for implementation at a higher level of abstraction than a synthesized, gate-level netlist. Proponents of RTL handoff point to the advantages ...
EDN

HDL-design challenges and philosophies for real-world ASIC implementations

New requirements for the MAC (medium-access control) and PHY (physical-layer interface) of a wireless-communications system can pose significant challenges for system designers looking to quickly get ...
Semiconductor Engineering

Connecting System-Level Flows To Implementation Tools

With the complexity explosion occurring in SoC design today, there is a relentless force to push design decisions further up in terms of abstraction. Resolving issues at the gate level is not possible ...
EDN

Video color space converter design using mixed-signal via-configurable ASICs

Today, many engineers find themselves involved in the development of mixed-signal products. While there may be a large section of digital logic in the design, the edges of the system tend to be very ...
Business Wire

Faraday Joins Intel Foundry Accelerator Design Services Alliance to Target Advanced Applications

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leader in ASIC design services and IP solutions, announces joining the Intel Foundry Accelerator Design Services, ...
Electronic Design

FPGAs Ride Tools Into ASIC Territory

When pondering your next-generation system design, you may ask yourself whether the spiraling mask costs have priced you out of the ASIC game. You'll perform the requisite analyses of performance ...
Business Wire

Menta Introduces the Industry’s First eFPGA Soft IP at the Design Automation Conference

SOPHIA-ANTIPOLIS, France--(BUSINESS WIRE)--Menta S.A.S., a premier supplier of embedded FPGA (eFPGA) solutions, today announced the industry’s first eFPGA soft IP offering, giving engineers greater ...
Design-Reuse

PCI Express Design Considerations -- RapidChip Platform ASIC vs. FPGA Design Efficiency

This paper describes the implementation differences of an IP core between FPGA and RapidChip® Platform ASIC technologies. By mapping the same complex, high-speed PCI Express core onto these two ...
Design-Reuse

EnSilica teams with BaySand to provide ASIC UltraShuttle-65 multi-project wafer customers with configurable IP solutions

EnSilica to provide BaySand’s customers with configurable eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...
SDxCentral

Marvell Adds Custom ASICs to Semiconductor Portfolio

ASICs, for all the advantages they offer, are an expensive and time-consuming endeavor. But do they have to be? That's the question semiconductor vendor Marvell has posed with the launch of its custom ...