Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
New Electronics

Aldec platform supports newest fpga devices

Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...
Business Wire

Aldec Releases Active-HDL 10.1 with 64-bit Simulation Support

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...
Electronic Design

Graphical Code Coverage Tool Speeds Design Debugging

Code Snooper, a code coverage software tool for use with the Active-HDL design and verification environment is integrated with the Active-HDL simulation kernel and does not require additional ...
EDN

Aldec blends SystemC, HDL debugging

SANTA CRUZ, Calif. — Expanding its capabilities for mixed-language simulation of ASICs and FPGAs, Aldec Corp. this week (Dec. 27) announced the release of Riviera 2004.12. New features include ...
EDN

Active-HDLTM provides advanced verification environment for all QuickLogic FPGA and ESP families

QuickLogic Corporation and Aldec, Inc.,announced that QuickLogic is integrating Aldec's Active-HDLTM Lite verification environment into its QuickWorks QuickLogic and Aldec have partnered to provide ...
Business Insider

QuickLogic Announces Partnership with Aldec for eFPGA Simulation Flow

SUNNYVALE, Calif., Feb. 20, 2018 /PRNewswire/ -- QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, display bridge and programmable ...