EDN

Applying Constrained-Random Verification to Microprocessors

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...
Electronic Design

Remove The Processor Dilemma From Constrained-Random Verification

Block-level verification has become a fairly mature technology over the past 10 years. All of the major EDA players support constrained-random stimulus generation in the simulation testbench. As part ...
EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
Design-Reuse

Users Employ Specman Constrained-Random Verification for Complex IP

Two recent customer examples have shown the effectiveness of Specman constrained-random verification for complex SoCs. Raimund Soenning, manager of hardware development for the Graphics Competence ...
Electronic Design

Remove The Processor Dilemma From Constrained-Random Verification (.PDF download)

Block-level verification has become a fairly mature technology over the past 10 years. All of the major EDA players support constrained-random stimulus generation in the simulation testbench ...