Arasan acheives the Industrys First ASIL-D Certification for its CAN XL IP Core

Arasan Chip Systems, the industry's leading provider of IP for Mobile and Automobile SoC's, announced today that its CAN XL ...
Business Wire

Panasonic Starts Licensing IP Core for Semiconductors Complying with the IEEE 1901–2020 International Standard

OSAKA, Japan--(BUSINESS WIRE)--Panasonic Corporation has begun licensing the HD-PLC TM 4 *1 IP core required for the design of semiconductors with technologies and functions that comply with the IEEE ...
EDN

IP cores from 4i2i fit Actel ASICs

Viterbi and Reed-Solomon encoder and decoder intellectual-property (IP) cores from 4i2i Communications Ltd. have been optimized for use with Actel Corp.'s nonvolatile, single-chip ProASICPlus, ...
New Electronics

Fraunhofer IPMS introduces 10G TSN endpoint IP core for high‑speed deterministic ethernet

Fraunhofer IPMS has developed a new 10G Time‑Sensitive Networking (TSN) endpoint IP core that’s been designed to meet growing demands for deterministic, high‑bandwidth Ethernet in automotive, ...
EDN

IP cores to be tailored for Magma flow

San Jose, Calif. – Tool vendor Magma Design Automation Inc. has formed a series of alliances with silicon intellectual-property providers to fit their IP into the Magma tool flow. Companies in the ...
SpaceNews

Sigma Space Picks DapTechnology’s FireLink 1394b IP Core for NASA R&D Project

DapTechnology, a world-leading supplier of advanced IEEE 1394 technology solutions to the aerospace, defense, industrial, automotive and consumer electronics markets announced today that Sigma Space ...
Business Wire

Alma Technologies Launches Scalable Encoder and Decoder Semiconductor IP for VESA DSC 1.2b Visually Lossless Compression

ATHENS, Greece--(BUSINESS WIRE)--IP Highlights: - Fully compliant with VESA DSC 1.2b and backwards compatible with DSC 1.1 - Ultra-low latency visually lossless image compression for all types of ...
Electronic Design

Turbocoder IP Cores Keep Bit-Error Rates Low

All three cores are available in synthesizable VHDL or Verilog and are verified using Artisan Components' TSMC 0.18-µm standard cell library. They come with cycle- and bit-accurate ANSI C++ or SystemC ...
Design-Reuse

DDR5/LPDDR5/DDR4 Combo PHY & Controller IP Core in 12FFC - Eliminating Memory Interface Risk

A breakthrough in memory subsystem integration is redefining performance, flexibility, and time-to-market for advanced SoC designs. A fully silicon-proven DDR5/LPDDR5/DDR4 Combo PHY & Controller IP ...
CNET

Nortel, Avici team on IP core routing

Marguerite Reardon started as a CNET News reporter in 2004, covering cellphone services, broadband, citywide Wi-Fi, the Net neutrality debate and the consolidation of the phone companies. Nortel ...