Semiconductor Engineering

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...
Morningstar

Spirent Brings Industry-First Benchmarking to Cloud-Native Infrastructure Testing

Spirent Communications plc (LSE:SPT), a leading provider of test and assurance solutions for next-generation devices and networks, today announced the introduction of benchmarking capabilities to the ...
Business Wire

Largest Ever CharIN Testival and Conference Provides a Unique, Comprehensive Proving Ground to Test EV Charging Security, Interoperability, and Communication

The three-and-a-half-day event, hosted by Lincoln Electric in Cleveland, OH, demonstrates the industry’s focus on improving the electric vehicle (EV) charging experience. The largest Testival held to ...
National Academies of Sciences%2c Engineering%2c and Medicine

Assessing the Physical and Technical Suitability of DoD Test and Evaluation Ranges and Infrastructure

The Department of Defense operates several ranges across all service branches to test the effectiveness of military systems. The DoD’s Office of Test and Evaluation (DOT&E) has asked the Board on Army ...