Electrical and Computer Engineering - Carnegie Mellon University

New Course Bridges Industry Gap in Hardware Verification

The Department of Electrical and Computer Engineering has developed a new Hardware Verification course that introduces students to the principles and practices used by verification engineers in ...
Semiconductor Engineering

Formal Verification of Security Properties On RTL Designs

A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. “Modern out-of-order ...
Design-Reuse

Survey of Chip Designers on the Value of Formal Verification Across the Spectrum of Applications

Over 50 engineers and engineering managers were surveyed at DAC 2009 by Jasper Design Automation as part of a market research and analysis program examining how designers use formal verification ...
Communications of the ACM

Formal Reasoning Meets LLMs: Toward AI for Mathematics and Verification

A marriage of formal methods and LLMs seeks to harness the strengths of both.
Nature

Formal Verification of Arithmetic Circuits

Formal verification of arithmetic circuits is a rigorous approach that employs mathematical techniques to ascertain the correctness of hardware designs implementing arithmetic operations. This ...
EDN

Formal property verification: A tale of two methods

The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM (Universal Verification ...
Semiconductor Engineering

Formal Verification’s Usefulness Widens

Formal verification is being deployed more often and in more places in chip designs as the number of possible interactions grows, and as those chips are used in more critical applications. In the past ...