EDN

Open’ ATE platforms must support parallel test

There is considerable ongoing discussion on how to contain exponentially increasing test costs for systems-on-chip (SoCs) and microprocessors. As the transistor geometry shrinks and more transistors ...
Semiconductor Engineering

Coping With Parallel Test Site-to-Site Variation

Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each ...
Business Wire

Keysight’s New Parallel Parametric Test System Delivers High Throughput and Cost-Effective Wafer Test

SANTA ROSA, Calif.--(BUSINESS WIRE)--Keysight Technologies, Inc. (NYSE: KEYS), a leading technology company that delivers advanced design and validation solutions to help accelerate innovation to ...
Electronic Design

Parallel Processing Techniques Reduce Cellular Test Time

According to several recent market studies, roughly 750 million cellular handsets were shipped in 2006. This quantity is likely to increase to more than one billion handsets by 2011. These numbers are ...
EDN

Semiconductor characterization software adds parallel test, parametric die sort features

Cleveland, Ohio — Keithley Instruments, Inc. has announced the availability of its Automated Characterization Suite (ACS) V3.2 software for semiconductor test and characterization at the device, wafer ...