Traditional planar NAND flash has had a long and illustrious run, but its time is over. Multiple manufacturers have announced they have no plans to pursue 2D NAND below the 15nm process node. Share on ...

For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence. The long-standing goal has been to keep foundry customers on a competitive price, ...

An integrated circuit (IC) technique developed by Fairchild Instruments in 1959 that creates transistors on a flat surface compared to the uneven surface of the earlier mesa process. The planar ...

Not everyone will move to finFETs, and even those that do won’t necessarily do it quickly. Foundries are moving quickly to capitalize on this trend. Competition is heating up in the leading-edge ...