Electronic Design

Clock Domain Crossing and Synchronizers (Part 2): Best Practices

As chip designs grow in complexity and face tighter power constraints, depending on a single clock domain is no longer ...
EDN

Multiple clock domain SoCs: Verification techniques

With technology advancement and introduction of more complex SOCs, data transfer between multiple clock domains is more frequent and demanding, and CDC design and verification becomes a more ...
Electronic Design

High-Speed Synchronizer and Distribution Board Locks In Up to 64 Channels

Fans of Pentek’s Quartz family of RFSoC FPGA boards will find broad usage for a new family member: the Model 5903, a 3U VPX high-speed synchronizer and distribution board. Fans of Pentek’s Quartz ...
EDN

Formal approach eases multiple clock design

Multiple, independent clocks are ubiquitous in system-on-chip (SoC) design. Most SoC devices have multiple interfaces, some following standards that use very different clock frequencies. Many modern ...